Latest Opening

FPGA Engineer : (Exp – 10 years +)

Domain knowledge – RTL, Hardware Validation, Hardware Verification, Communication Protocol like – Ethernet, PCI. High Speed like SERDES
Tool – Any FPGA vendor
Location: Delhi NCR
Please contact me at nivesh@techadityaa.in

Hardware and PCB Board Design Engineer: (Exp – 2-3 years +)

Domain knowledge – Digital wireless communication, Digital Electronics and Signal processing.
Exp in designing high Speed PCB up to 24 layers Analytical knowledge of signal integrity and exp in both pre-layout and post layout
Tool – Mentor / Cadence
Location: Delhi NCR
Please contact me at nivesh@techadityaa.in

Hardware verification Engineer: (Exp – 2-3 years +)

Domain Knowledge – Digital wireless communication, Digital Electronics and Signal processing.
Skill Set – Verification in FPGA development Cycle, System Verilog /Verilog or VHDL Work on Highly industry Standard tool.
Location: Delhi NCR
Please contact me at nivesh@techadityaa.in

DSP FPGA Engineer: (Exp – 2-3 years +)

Domain knowledge – Digital wireless communication, Digital Electronics and Signal processing.
Skill Set- Matlab Simulink, HDL- Verilog /VHDL
Platform – XILINX
Optional – Scripting – BASH/TCL
Location: Delhi NCR
Please contact me at nivesh@techadityaa.in

Embedded FPGA Engineer: (Exp – 2-3 years +)

Domain Knowledge – ARM Processor Architecture, Digital Electronics, Wireless Communication, Knowledge of TCP IP stack
Skill Set – C/C++, Open CV , Python, Linux Platform or .Net Preference – Work on ZYNQ Platform
Location: Delhi NCR
Please contact me at nivesh@techadityaa.in

Demo and Technical Support on FPGA Product i.e. Pre-Technical sales and Post- Technical sales support.

Skill set Required-
• HDL- Verilog / VHDL
• Programming – C & Embedded C (Basic Understanding)
• Processor – ARM or Any Microcontroller (Basic
• Knowledge of Signal Processing – Like DSP and Image or Video processing (Optional)
• Engineering Domain Knowledge – Communication Engineering
• Tools EXP- XILINX – ISE/VIVADO or Altera – Quartus Flow , Similarly for Lattice & Actel
Experience – 2 to 5 years in FPGA Design or in FAE
Qualification : M.Tech/B.Tech in ECE or VLSI can apply .
Please contact me at nivesh@techadityaa.in

R&D Engineer

1. Experience required: 4 to 6 yrs.
2. Skills in handling image, video processing/ codec/ algorithms/ statistics
3. Knowledge of machine learning
4. Algorithm design
5. Proficient skills in MatLab software, OpenCV, C language, Python etc.
Location : Noida
Please contact me at nivesh@techadityaa.in

FPGA

1. Experience required: 3 to 4 yrs.
2. Knowledge of 3GPP standards for LTE TDD/FDD, UMTS technologies.
3. Must have a strong knowledge of RTLs (vhdl) + TCL scripting.
4. Xilinx IP integration, debugging and verification.
5. Must have knowledge of AXI Interfaces, uart, spi, iic.
6. Knowledge to DSP will be a plus.
7. KEY SKILLS: Xilinx Tools, Vivado, VHDL, Telecom, FPGA

ASIC/FPGA Design Engineer

Experience : 4 yrs.
Skills : Verilog or VHDL for Xilinx or Altera Experience with communication standards, such as Ethernet, OTN, Interlaken
Location : Noida
Salary : Best in Industry
Please contact me at nivesh@techadityaa.in

ASIC/FPGA Design Engineer (Sr.)

Experience : 7 yrs.
Skills : Verilog or VHDL for Xilinx or Altera Experience with communication standards, such as Ethernet, OTN, Interlaken
Location : Noida
Salary : Best in Industry
Please contact me at nivesh@techadityaa.in